On Sat, Feb 20, 2010 at 07:51:20PM +0100, Hauke Mehrtens wrote: > Ignoring the last page when ddr size is 128M. Cached > accesses to last page is causing the processor to prefetch > using address above 128M stepping out of the ddr address > space. Is this a hardware issue prefetching issue? The kernel should not try CPU prefetch instructions at all on non-coherent CPUs such as the BCM47xx. Ralf
