On Mon, Feb 01, 2010 at 04:10:26PM -0800, Guenter Roeck wrote:
> > > + if (cpu_has_64bits) {
> > > + write_c0_entryhi(0xfffffffffffff000ULL);
> >
> > macro indicated that we need to avoid hazards here on R4000.
A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but
will read from the same register on stage 4 which leaves a window of
2 instructions, that is 2 NOP instructions needed.
> > Perhaps adding:
> >
> > back_to_back_c0_hazard();
> >
> Compiler already added a nop, so I thought it wasn't necessary.
> Doesn't hurt either, so I'll put it in.
This probe is needed as per MIPSxx architecture spec and several CPUs will
missbehave without it. The 74K which of course is 32-bit but it
illustrates the issue might even issue these instructions out of order.
back_to_back_c0_hazard will expand into a suitable sequence to handle
the pipeline hazard. And we can't trust on the compiler doing the right
thing here; as explained above we might need multiple nops and some CPUs
will need other instructions to deal with the hazard, for example a number
of SSNOPs or an EHB instruction.
Ralf
