On Mon, Dec 21, 2009 at 05:49:22PM -0800, David VomLehn wrote: > The MIPS processor is limited to 64 external interrupt sources. Using a > greater number without IRQ sharing requires reading platform-specific > registers. On such platforms, reading the IntCtl register to determine > which interrupt corresponds to a timer interrupt will not work. > > On MIPSR2 systems there is a solution--the TI bit in the Cause register, > specifically indicates that a timer interrupt has occured. This patch > uses that bit to detect interrupts for MIPSR2 processors, which may be > expected to work regardless of how the timer interrupt may be routed > in the hardware. I think this isn't relevant for any currently in-tree supported platforms (?) so I've queued this for 2.6.34. Thanks, Ralf
