On Tue, Nov 17, 2009 at 04:59:59PM +0800, figo zhang wrote: > > > why this right shift 6 bits? this 6 bits contain some important bit, such > > > as: > > > C: [bit3~5]: cohereny attribute of page > > > > No, the low 6 bits contain other information maintained by the kernel. > > Shifting right by 6 bits is used to drop these software bits. The > > hardware bits are stored in bits 6 and up in a pte so the shift operation > > is going to move them into the right place. > > > > But i have see the kernel code: include/asm-mips/pgtable-bits.h: > #define _CACHE_UNCACHED (2<<3) > #define _CACHE_CACHABLE_NONCOHERENT (3<<3) > #define _CACHE_CACHABLE_COW (3<<3) /* Au1x */ This is code for the special case where CONFIG_64BIT_PHYS_ADDR and CONFIG_CPU_MIPS32 are both defined. In that case tlb-r4k.c also won't do shifting. > in include/asm-mips/pgtbale.h: > #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ > PAGE_CACHABLE_DEFAULT) > > so, if i set a page attrubite is PAGE_READONLY, this attribute will set to > pte , right? so , > why it should shift 6 bits? > > > > > > D: > > > V: > > > G: > > > > > > and how the kernel write the this 6 bit to entrylo0/1 register? > > > > A TLB write instruction about 5 lines further down in the code. > > > > which function write those 6 bits to register? tlb_write_indexed() ? if i > want set pages cache attribute is uncached/write-back , how it can set it > correctly to MIPS? See drivers/char/mem.c; search for pgprot_noncached(). This is where for uncached mmaps pick the apropriate page protection and cache bits. Several other drivers may do equivalent things. Ralf
