This set of patches optimizes TLB handling in mips64r2 processors. If we have the mips64r2 ISA available, we can do enough bit twiddling with out using a scratch register that it become possible and desirable to carry the PGD pointer in c0_context rather than having to always load it from memory. The first patch adds some instructions to uasm that are needed by the second patch. The second patch contains the main changes. I will reply with the two patches. David Daney (2): MIPS: Add drotr and dins instructions to uasm. MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. arch/mips/Kconfig | 3 +++ arch/mips/include/asm/mmu_context.h | 29 ++++++++++++++++++++++++++++- arch/mips/include/asm/stackframe.h | 20 ++++++++++---------- arch/mips/mm/init.c | 2 ++ arch/mips/mm/tlbex.c | 28 +++++++++++++++++++++++++--- arch/mips/mm/uasm.c | 16 +++++++++++++--- arch/mips/mm/uasm.h | 7 +++++++ 7 files changed, 88 insertions(+), 17 deletions(-)
