Markus Gothe wrote:
Is this just the HCD part AND is it tested to be endian safe?
This particular patch just adds platform devices for the Octeon SOC.
The main patch (Patch 2/2) can be seen here:
http://marc.info/?l=linux-mips&m=125502126531841&w=2
For some reason it hasn't come out on linux-usb yet.
If you look at '[PATCH 2/2] USB: Add HCD for Octeon SOC', you will see
that it has the hcd support. I have omitted pcd support from this set,
as I am working towards getting hcd mergable first.
As for endian issues, the current Octeon support in the kernel is for
big-endian only, so since the usb hardware is on the same chip as the
CPU, endian safety is not currently an issue. I have heard rumors that
some ralink and PPC variants have the same controller, but I have no way
of confirming this or even testing the code as I don't have that hardware.
Think of a 16-bits BE GIO-bus connected to the LE-32 HCD. (It's an
incredible mess to debug that kind of setup...)
Indeed.
David Daney
//Markus Gothe - The panamahat hacker
On 8 Oct 2009, at 02:15, David Daney wrote:
Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
---
arch/mips/cavium-octeon/octeon-platform.c | 105 ++
arch/mips/include/asm/octeon/cvmx-usbcx-defs.h | 1199
++++++++++++++++++++++++
[...]
