On Mon, Sep 7, 2009 at 3:26 AM, Ralf Baechle<ralf@xxxxxxxxxxxxxx> wrote: > Too complicated. The fault is happening because the non-SMTC code is trying > to be terribly clever and pre-loading the TLB with a new wired entry. On > SMTC where multiple processors are sharing a single TLB are more careful > approach is needed so the code does a TLB probe and carefully and re-uses > an existing entry, if any. Which happens to be just what we need. > > So how about below - only compile tested - patch? That is an interesting idea. However, I am not sure we want the IPI ISR to overwrite copy_user_highpage()'s TLB entry. That means that when the interrupt returns, our coherent mapping will likely point to a different page. It will avoid the machine check exception, but it will potentially cause silent, intermittent data corruption instead. Taking another cue from the SMTC implementation, though - my v2 patch adds an extra set of fixmap addresses for the in_interrupt() case, avoiding the VA conflict entirely. What do you think? I tested this scheme on non-SMTC. I suspect that the same change is required for MT + MP cores like the 1004K, but probably not MT only cores like 34K which don't use cacheop IPIs.
