This patch adds basic support for the bcm96345gw2 reference design (e.g: Siemens SE515) and make it boot up to user-space. Integrated peripherals support needs some more work. Signed-off-by: Florian Fainelli <florian@xxxxxxxxxxx> --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index e639438..17a8636 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -124,6 +124,16 @@ static struct board_info __initdata board_96338w = { #endif /* + * known 6345 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6345 +static struct board_info __initdata board_96345gw2 = { + .name = "96345GW2", + .expected_cpu_id = 0x6345, +}; +#endif + +/* * known 6348 boards */ #ifdef CONFIG_BCM63XX_CPU_6348 @@ -536,6 +546,9 @@ static const struct board_info __initdata *bcm963xx_boards[] = { &board_96338gw, &board_96338w, #endif +#ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +#endif #ifdef CONFIG_BCM63XX_CPU_6348 &board_96348r, &board_96348gw, @@ -562,10 +575,16 @@ void __init board_prom_init(void) u8 *boot_addr, *cfe, *p; char cfe_version[32]; u32 val; - - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + + /* read base address of boot chip select (0) + * 6345 does not have MPI but boots from standard + * MIPS Flash address */ + if (BCMCPU_IS_6345()) + val = 0x1fc00000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + } boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ @@ -812,8 +831,12 @@ int __init board_register_devices(void) #endif /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + if (BCMCPU_IS_6345()) + val = 0x1fc00000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + } mtd_resources[0].start = val; mtd_resources[0].end = 0x1FFFFFFF;