On Tue, Jun 30, 2009 at 06:13:41PM -0700, David Daney wrote: > The problem with CPU_MIPS64_R2 in the kernel is that it means two > unrelated things: > > 1) The cpu can execute all mips64r2 ISA instructions. > > 2) The cpu requires that all worse case cache and execution hazards are > handled. > > In the case of the Octeon processors, #1 is true, but we can get better > performance by omitting many of the hazard barriers because they are > unneeded. The most performance sensitive hazard barriers are the ones in the TLB exception handlers and they're now being handled in C code in tlbex.c which mostly does runtime decissions. I suspect the remaining hazard barriers are not a big performance thing anymore. Ralf
