On Tue, 30 Jun 2009, David Daney wrote: > The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated > things: > > 1) The cpu can execute all mips64r2 ISA instructions. > > 2) The cpu requires that all worse case cache and execution hazards are > handled. > > In the case of the Octeon processors, #1 is true, but we can get better > performance by omitting many of the hazard barriers because they are unneeded. Which is why I think a split of the semantics would be a good idea. Maciej
