Some CPUs have implementation dependent rdhwr registers. Allow them
to be enabled on a per CPU basis.
Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
---
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/kernel/traps.c | 2 +-
2 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1cba4b2..8ab1d12 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -234,4 +234,8 @@
#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits 0
+#endif
+
#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c3cc42e..efcb509 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1541,7 +1541,7 @@ void __cpuinit per_cpu_trap_init(void)
status_set);
if (cpu_has_mips_r2) {
- unsigned int enable = 0x0000000f;
+ unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
if (!noulri && cpu_has_userlocal)
enable |= (1 << 29);
--
1.6.0.6
