On Tue, May 12, 2009 at 12:41:54PM -0700, David Daney wrote: > The Octeon has no execution hazards, so we can remove them and save an > instruction per TLB handler invocation. > > Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx> > --- > .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > index 04ce6e6..bb291f4 100644 > --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h > @@ -47,6 +47,7 @@ > #define cpu_has_mips32r2 0 > #define cpu_has_mips64r1 0 > #define cpu_has_mips64r2 1 > +#define cpu_has_mips_r2_exec_hazard 0 > #define cpu_has_dsp 0 > #define cpu_has_mipsmt 0 > #define cpu_has_userlocal 0 > -- > 1.6.0.6 Simple enough that even I can understand it. Reviewed by: David VomLehn <dvomlehn@xxxxxxxxx>
