Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.
Signed-off-by: David Daney <ddaney@xxxxxxxxxxxxxxxxxx>
---
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/mm/tlbex.c | 3 ++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f8..1cba4b2 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2)
+#ifndef cpu_has_mips_r2_exec_hazard
+#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
+#endif
+
/*
* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 3548acf..4108674 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -258,7 +258,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
}
if (cpu_has_mips_r2) {
- uasm_i_ehb(p);
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(p);
tlbw(p);
return;
}
--
1.6.0.6
