The CHAR register is 64-bit width but 32-bit kernel uses its lower
part only. Be careful of initializing it.
Signed-off-by: Atsushi Nemoto <anemo@xxxxxxxxxxxxx>
---
This patch is against linux-mips.org linux-queue tree.
Please queue this or fold into "DMA: TXx9 Soc DMA Controller driver" patch.
drivers/dma/txx9dmac.c | 12 +++++++++++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index c655350..9aa9ea9 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -72,6 +72,16 @@ static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
channel64_writel(dc, CHAR, val);
}
+static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
+{
+#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
+ channel64_writel(dc, CHAR, 0);
+ channel64_writel(dc, __pad_CHAR, 0);
+#else
+ channel64_writeq(dc, CHAR, 0);
+#endif
+}
+
static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
{
if (is_dmac64(dc))
@@ -318,7 +328,7 @@ static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
{
channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
if (is_dmac64(dc)) {
- channel_writeq(dc, CHAR, 0);
+ channel64_clear_CHAR(dc);
channel_writeq(dc, SAR, 0);
channel_writeq(dc, DAR, 0);
} else {
--
1.5.6.3
