As per the subject, this set adds support for PCI and PCIe to the
Cavium OCTEON processor support.
The first patch is just register definitions for the PCI related
hardware.
The second contains the drivers and hooks them up. The DMA mapping
code needs to do quite a bit to handle the PCI. Interrupt handling
was already present, but we need a couple of more include files.
Other than that, it is all PCI driver things.
I will reply with the two patches.
David Daney (2):
MIPS: Add register definitions for PCI.
MIPS: Add Cavium OCTEON PCI support.
arch/mips/Kconfig | 2 +
arch/mips/cavium-octeon/Makefile | 4 +
arch/mips/cavium-octeon/dma-octeon.c | 311 +++-
arch/mips/cavium-octeon/executive/Makefile | 1 +
.../cavium-octeon/executive/cvmx-helper-errata.c | 70 +
.../cavium-octeon/executive/cvmx-helper-jtag.c | 144 ++
arch/mips/cavium-octeon/msi.c | 288 +++
arch/mips/cavium-octeon/octeon-irq.c | 2 +
arch/mips/cavium-octeon/pci-common.c | 137 ++
arch/mips/cavium-octeon/pci-common.h | 39 +
arch/mips/cavium-octeon/pci.c | 568 +++++
arch/mips/cavium-octeon/pcie.c | 1370 +++++++++++
arch/mips/include/asm/octeon/cvmx-helper-errata.h | 33 +
arch/mips/include/asm/octeon/cvmx-helper-jtag.h | 43 +
arch/mips/include/asm/octeon/cvmx-npei-defs.h | 2560
++++++++++++++++++++
arch/mips/include/asm/octeon/cvmx-npi-defs.h | 1735 +++++++++++++
arch/mips/include/asm/octeon/cvmx-pci-defs.h | 1645 +++++++++++++
arch/mips/include/asm/octeon/cvmx-pcieep-defs.h | 1365 +++++++++++
arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 1397 +++++++++++
arch/mips/include/asm/octeon/cvmx-pescx-defs.h | 410 ++++
arch/mips/include/asm/octeon/cvmx-pexp-defs.h | 229 ++
arch/mips/include/asm/octeon/cvmx.h | 12 +
arch/mips/include/asm/octeon/octeon.h | 2 +
23 files changed, 12365 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
create mode 100644 arch/mips/cavium-octeon/msi.c
create mode 100644 arch/mips/cavium-octeon/pci-common.c
create mode 100644 arch/mips/cavium-octeon/pci-common.h
create mode 100644 arch/mips/cavium-octeon/pci.c
create mode 100644 arch/mips/cavium-octeon/pcie.c
create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-errata.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-jtag.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-npei-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-npi-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pci-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pescx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pexp-defs.h
