Manuel Lauss wrote:
> I'm curious: Is it required to use the CP0 counter for SMTC kernels, or
> could the SMTC-specific parts somehow be abstracted out and called by
> other timer backends? (for a hypothetical SMTC-enhanced Alchemy core)
>
Theoretically, one could, but it would require a major rewrite of
cevt-smtc.c, which implements multiple virtual per-CPU one-shot timer
interrupts multiplexed off a single timer interrupt source (the SMTC
environment has a couple of quirks that make the generic timer broadcast
code pretty useless). The concept could be applied to arbitrary
counter-based interrupts, but for simplicity and performance, the code
assumes MIPS32 Count/Compare, and to minimize redundant source code, it
uses common functions with cevt-r4k.c wherever possible (that's why
there are those #ifdef MIPS_MT_SMTC's in cevt-r4k.c).
Regards,
Kevin K.
