On Tue, Mar 10, 2009 at 12:18:28PM -0700, VomLehn wrote: > > > +config CP0_COUNT_NDELAY > > > + bool "Use coprocessor 0 Count register for ndelay functionality" > > > + default n > > > > Does there need to be some sort of depends here to cover off any > > limitations where it is known that it won't work? > > I don't have the breadth of knowledge required to say what processors have > a CP0 Count register. Any suggestions? All MIPS III, MIPS IV, MIPS32 and MIPS64 processors have a 32-bit count register which typically is clocked at half the maximum instruction issue rate, more rarely at the full rate. A few processors like the RM53230 family can select the increment rate at reset-time to either the full or half instruction issue rate. Others have the option of totally halting it in special low-power, low-performance modes. The count rate might also be affected by clock scaling. Ralf
