On Sun, 08 Feb 2009 14:52:48 +0300, Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx> wrote: > >> + __ide_flush_dcache_range((unsigned long)buf, count * 2); > >> +} > > > > Atsushi, does TX49 really suffer from the issue that these flushes > > are trying to address? > > Well, looking thru the TX4939 thread, it appears that I've asked this > question already. Isn't this related to VIVT caches? No, TX49 has VIPT cache. It is related to D-cache aliasing on PIO. My first attempt to fix this issue goes back to 2004: http://www.linux-mips.org/archives/linux-mips/2004-03/msg00185.html And more generic lengthy discussion can be found on (as mentioned in the previous tx4939 thread): http://lkml.org/lkml/2006/1/13/156 --- Atsushi Nemoto
