> The idea here is that we have two issues with prefetching: > > o Prefetching beyond the end of the source or destination range on a > in-coherent range might bring back stale values from a DMA I/O > buffer resulting in data corruption. Hardware DMA coherency will > avoid this issue. > > o IP27 has full blown hardware coherency. Historically > CONFIG_DMA_COHERENT > was not able to cope with something of the complexity of IP27, so > there was a separate CONFIG_DMA_IP27 and the broken logic > expression > was meant to treat CONFIG_DMA_COHERENT and CONFIG_DMA_IP27 the same > as for prefetching. > > o Prefetching beyond the end of physical memory can cause > exceptions on > some systems. The Malta has this problem. > > Thus no prefetching on Malta or non-coherent systems. > > Ralf It seems to me as though we could avoid the first and third problems with a memcpy that doesn't prefetch past the end of the buffer, the thought being that if we are reading or writing a memory region, we really shouldn't be doing DMA to or from that location. This would probably be slightly suboptimal, performance-wise, for those systems that do have DMA coherence. It seems as though we could have two mutually exclusive versions, selectable via the CONFIG_DMA_COHERENT flag. For those of us without DMA coherence, it would probably give our memcpy performance a bit of a kick in the pants over using no prefetch at all. If this makes sense, we might be able to sign up to do the work. Anyone have a good, caching-aware memcpy test? -- David VomLehn, dvomlehn@xxxxxxxxx
