On Fri, 21 Nov 2008, Ralf Baechle wrote:
> MIPS ISA newer than MIPS I also have conditional break codes allowing
> something like this:
>
> #define BUG_ON(condition) \
> do { \
> __asm__ __volatile__("tne $0, %0, %1" \
> : : "r" (condition), "i" (BRK_BUG)); \
> } while (0)
>
> that is test of condition and the trap as a single instruction. Note there
> are break and trap instructions on MIPS and they are basically doing the
> same job ...
GCC is actually smart enough to combine sequences like:
if (something)
__builtin_trap();
into appropriate conditional trap instructions on MIPS. As noted by David
trap codes other than the default cannot be emitted this way though.
Maciej
