On Fri, Jun 27, 2008 at 11:52:26PM +0200, Thomas Bogendoerfer wrote: > The introduction of a real dma cache invalidate makes it important > to have a correct cache line size, otherwise the kernel will gives > out two memory segment, which might share one cache line. The R4400 > Indy/Indigo2 CPU modules are using a second level cache line size > of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for > IP22. Thanks, applied. I also think this missconfiguration is worth an additional runtime check; the consequence of that kind of bug are subtle and painful to debug. Ralf
