Ralf Baechle wrote:
On Mon, Jun 09, 2008 at 09:32:59PM +0200, Kevin D. Kissell wrote:
That is correct, though there has long been interest in having XI/RI as an option for non-SmartMIPS cores and I would not be surprised if sooner or later it became more generally available.
Cavium has it in their 64-bit core. I haven't verified this in the docs
but apparently it is meant to be compatible with the old SmartMIPS ASE
for MIPS32.
Do check the documentation. I can't comment officially, but I can
observe that,
in the hypothetical case where you'd want XI/RI semantics in a 64-bit
processor,
you might use exactly the same semantics (and therefore the same kernel
C code
support), but you might want to use different bits for XI/RI in a
64-bit TLB entry
than in a 32-bit TLB entry (and therefore different header file
definitions).
Regards,
Kevin K.
