On Thu, Oct 25, 2007 at 04:59:12PM +0100, Thiemo Seufer wrote:
> currently the kernel panics when it boots on an unknown CPU model
> (with an unknown PRID). Based on the assumption that the majority
> of newly supported CPU will conform to Release 2 standard, I wrote
> the appended patch which handles unknown CPUs as R2. It isn't
> completely bulletproof, as (yet unsupported) non-R1/R2 CPUs may
> use the AT config bits for different purposes. I still think this
> is good enough a test.
>
> This patch allows me to boot Linux on a "generic" MIPS64R2 Qemu
> without making up a potentially conflicting PRID. All-zeroes
> like for other undefined fields does fine.
It's a little more elegant with cpu_has_mips_r2. So how about below patch.
Ralf
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a61246d..91a7380 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -935,14 +935,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
tlbw(p);
break;
- case CPU_4KEC:
- case CPU_24K:
- case CPU_34K:
- case CPU_74K:
- i_ehb(p);
- tlbw(p);
- break;
-
case CPU_RM9000:
/*
* When the JTLB is updated by tlbwi or tlbwr, a subsequent
@@ -982,8 +974,13 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
break;
default:
- panic("No TLB refill handler yet (CPU type: %d)",
- current_cpu_data.cputype);
+ /* Panic if this isn't a Release 2 CPU. */
+ if (!cpu_has_mips_r2)
+ panic("No TLB refill handler yet (CPU type: %d)",
+ current_cpu_data.cputype);
+ /* fall through */
+ i_ehb(p);
+ tlbw(p);
break;
}
}
