On Tue, Oct 09, 2007 at 10:05:30PM +0100, Alan Cox wrote: > > Before I dive into this, does any of this ring a bell for anyone? > > I'm using the ide-cs driver, TI yenta cardbus adapter driver, and sibyte > > everything else. > > That has cache coherency painted all over it in bright flashing letters. The Sibyte SOCs have hardware cache coherency and physically indeded D-caches which makes I/O pretty much a nobrainer. I-cache coherency is the thing that really needs babysitting on Sibyte and the Sibyte I-caches are of a somewhat rare kind by being VIVT plus an additional address space tag. Mostly because of code duplication the Sibyte cachecode has its nice damp and dark corner where it did bitrot away for a while. Thiemo and I recently found the standard R4000 cache code to work more reliable for Sibyte so we're getting rid of it for 2.6.24. The patch is in 06e523e89ec0322c4abcf41533d5380dfcd81f73. It can easily be backported to older kernels so I suggest trying this one. (As collateral damage 06e523e89ec0322c4abcf41533d5380dfcd81f73 breaks support for pass 1 BCM1250 parts. But it seems I'm the last one with one of those ...) Ralf
