Use bus numbering when addressing device with MACE chipset
in order to support PCI bridges.
Changes in chkslot() and mkaddr() #defines.
Signed-off-by: Giuseppe Sacco <eppesuig@xxxxxxxxxx>
---
Hi Ralf,
I managed to create a patch against current 2.6.23-rc9 git tree
for supporting PCI bridges on SGI ip32 machines.
This is my first kernel patch, so I am usure about the correct way
to send a patch. Please let me know if anything is wrong.
Bye,
Giuseppe
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index 8008e31..18a7159 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -31,20 +31,21 @@
#define chkslot(_bus,_devfn) \
do { \
- if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \
- || PCI_SLOT (_devfn) > 3) \
+ if ((_bus)->number > 1 || \
+ ((_bus)->number == 0 && (PCI_SLOT (_devfn) < 1 \
+ || PCI_SLOT (_devfn) > 3))) \
return PCIBIOS_DEVICE_NOT_FOUND; \
} while (0)
-#define mkaddr(_devfn, _reg) \
-((((_devfn) & 0xffUL) << 8) | ((_reg) & 0xfcUL))
+#define mkaddr(_bus, _devfn, _reg) \
+((((_bus)->number & 0xffUL) << 16) | (((_devfn) & 0xffUL) << 8) | ((_reg) & 0xfcUL))
static int
mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
chkslot(bus, devfn);
- mace->pci.config_addr = mkaddr(devfn, reg);
+ mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
*val = mace->pci.config_data.b[(reg & 3) ^ 3];
@@ -67,7 +68,7 @@ mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 val)
{
chkslot(bus, devfn);
- mace->pci.config_addr = mkaddr(devfn, reg);
+ mace->pci.config_addr = mkaddr(bus, devfn, reg);
switch (size) {
case 1:
mace->pci.config_data.b[(reg & 3) ^ 3] = val;
