On Tue, Oct 02, 2007 at 10:57:24PM +0200, Aurelien Jarno wrote: > From: Aurelien Jarno <aurelien@xxxxxxxxxxx> > Date: Tue, 02 Oct 2007 22:57:24 +0200 > To: Alan Cox <alan@xxxxxxxxxxxxxxxxxxx> > CC: qemu-devel@xxxxxxxxxx, linux-mips@xxxxxxxxxxxxxx > Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel > Content-Type: text/plain; charset=ISO-8859-1 > > Alan Cox a écrit : > >> Well on real hardware, the instruction rate and the timer are linked: > >> the timer run at half the speed of the CPU. As the corresponding > >> assembly code is very small, only uses registers and is run in kernel > >> mode, you know for sure that 48 cycles is more than enough. > > > > What happens on NMI or if you take an ECC exception and scrubbing stall > > off the memory controller while loading part of that cache line of code > > into memory ? > > > > The code returns -ETIME, and the function is run again with the minimum > delay. > > So as long as you don't have an exception every time, the code works. The current setting should be safe on real hardware - but a value of just 48 cycles for max_delta_ns is probably lower than the lowest useful value, so I don't mind raising it. This number really is a tunable. Ralf
