On Tue, 2 Oct 2007, Giuseppe Sacco wrote: > PCI: Fixups for bus 0000:00 > PCI: Scanning behind PCI bridge 0000:00:03.0, config ffffff, pass 0 > PCI: Scanning behind PCI bridge 0000:00:03.0, config 000000, pass 1 > PCI: Scanning bus 0000:01 > PCI: Fixups for bus 0000:01 > PCI: Bus scan for 0000:01 returning with max=01 > PCI: Bus scan for 0000:00 returning with max=01 So it looks like the generic PCI code does scan behind the bridge at 0000:00:03.0, but nothing is found. So the first obvious question is: "Does your host bridge (or actually code that handles it) correctly generate type 1 PCI configuration cycles?" It looks like arch/mips/pci/ops-mace.c is the place to look for possible breakage. Well, actually chkslot() there is the obvious answer. It is probably easy to fix, but for somebody with documentation or at least the right piece of hardware, so I do not qualify, I am afraid. Sorry. Failing anybody else, you may be able to figure it out yourself -- you probably need to stick bus->number into mace->pci.config_addr somewhere. Try bits 23:16 as the obvious first guess. Maciej
