Hi there, in the following mips 32bit atomic cmp_xchg api, I was
wondering why there is no nop after the two branch instructions. Does
this introduce a bug, or is it a "feature" in the code to use the
delay slot for an instructino to execut something whether or not they
take the branch.
#define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, acq) \
__asm__ __volatile__ ( \
".set push\n\t" \
MIPS_PUSH_MIPS2 \
rel "\n" \
"1:\t" \
"ll %0,%4\n\t" \
"move %1,$0\n\t" \
"bne %0,%2,2f\n\t" \
"move %1,%3\n\t" \
"sc %1,%4\n\t" \
"beqz %1,1b\n" \
acq "\n\t" \
".set pop\n" \
"2:\n\t" \
: "=&r" (__prev), "=&r" (__cmp) \
: "r" (oldval), "r" (newval), "m" (*mem) \
: "memory")
