Hi all, I have playing around with a Malta board which has a MIPS32 24KEc core (PR.ID = 2.0.1). I was testing the CACHE instruction and I observed the following *weird* behavior: I try to lock a given range of addresses within the cache. I tried to do so with both operations (i.e. Index store tag and Fetch&Lock). What I observe is that the Fetch&Lock is locking much *less* lines than what the index store tag does. Is there anyone who is aware of any constrains/errata regarding this issue? Best regards, -- Mohamed A. Bamakhrama Am Schaeferanger 15, room 035 85764 Oberschleissheim, Germany Email: bamakhra@xxxxxxxxxx Web: http://home.cs.tum.edu/~bamakhra/ Mobile: +49-160-9349-2711
