Daniel Laird wrote: > Update Patch > > Fix known bug with MIPS core when using TLB on NXP/Philips PNX8550 > > Signed-off-by: Daniel Laird <daniel.j.laird@xxxxxxx> > --- > tlb-r4k.c | 4 +++ > tlbex.c | 71 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > --- > Index: linux-2.6.22.1/arch/mips/mm/tlbex.c > =================================================================== > --- linux-2.6.22.1/arch/mips/mm/tlbex.c (revision 8) > +++ linux-2.6.22.1/arch/mips/mm/tlbex.c (working copy) > @@ -435,6 +435,9 @@ > label_nopage_tlbm, > label_smp_pgtable_change, > label_r3000_write_probe_fail, > +#ifdef CONFIG_PNX8550 > + label_pnx8550_bac_reset > +#endif Please don't use #ifdef where it isn't needed ... [snip] > +static void __init build_pnx8550_bug_fix( u32 **p, struct label **l, > struct reloc **r) > +{ > +#define MFC0(_reg, _cp, _sel) \ > + ((cop0_op) << OP_SH \ > + | (mfc_op) << RS_SH \ > + | (_reg) << RT_SH \ > + | (_cp) << RD_SH \ > + | (_sel)) > + > +#define MTC0(_reg, _cp, _sel) \ > + ((cop0_op) << OP_SH \ > + | (mtc_op) << RS_SH \ > + | (_reg) << RT_SH \ > + | (_cp) << RD_SH \ > + | (_sel)) ... don't reinvent the wheel ... [snip] > @@ -1261,8 +1328,12 @@ > build_get_ptep(&p, K0, K1); > build_update_entries(&p, K0, K1); > +#ifndef CONFIG_PNX8550 > build_tlb_write_entry(&p, &l, &r, tlb_random); > l_leave(&l, p); > +#else > + build_pnx8550_bug_fix(&p, &l, &r); > +#endif ... and make that a runtime check. > i_eret(&p); /* return from trap */ > #ifdef CONFIG_64BIT > Index: linux-2.6.22.1/arch/mips/mm/tlb-r4k.c > =================================================================== > --- linux-2.6.22.1/arch/mips/mm/tlb-r4k.c (revision 8) > +++ linux-2.6.22.1/arch/mips/mm/tlb-r4k.c (working copy) > @@ -456,7 +456,11 @@ > */ > probe_tlb(config); > write_c0_pagemask(PM_DEFAULT_MASK); > +#ifdef CONFIG_SOC_PNX8550 > + write_c0_wired(11); > +#else > write_c0_wired(0); > +#endif 11 wired entries sounds excessive to me. Is it really necessary to kill that much performance? Thiemo