The attached patch fixes some problems with the linux-mips.org
2.6.21 kernel for SMTC kernels for the Malta platform.
The fix to smtc.c just eliminates a warning that crept in.
The fixes to traps.c eliminate a hypothetical problem with
out-of-bounds arguments (which were being reported, but acted
upon anyway, which was somewhat insane) and a real one with
PageMask going uninitialized in VPE 1 on any MIPS MT processor
that doesn't reset PageMask to a sane value, which the archtecture
does not require.
The restoration of the #define in mips-boards/generic/time.c
is necessary to make the Malta SMTC kernel build. If whoever
deleted it has a good reason for it not to be done the way it's
done, that's OK, but *some* definition must be provided.
Regards,
Kevin K.
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index b361edb..21eb599 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -611,12 +611,12 @@ void smtc_cpus_done(void)
int setup_irq_smtc(unsigned int irq, struct irqaction * new,
unsigned long hwmask)
{
+#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
unsigned int vpe = current_cpu_data.vpe_id;
- irq_hwmask[irq] = hwmask;
-#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1;
#endif
+ irq_hwmask[irq] = hwmask;
return setup_irq(irq, new);
}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 48c8b25..b42db85 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1190,10 +1190,12 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
memcpy (b, &except_vec_vi, handler_len);
#ifdef CONFIG_MIPS_MT_SMTC
- if (n > 7)
+ if (n < 8) {
+ w = (u32 *)(b + mori_offset);
+ *w = (*w & 0xffff0000) | (0x100 << n);
+ } else {
printk("Vector index %d exceeds SMTC maximum\n", n);
- w = (u32 *)(b + mori_offset);
- *w = (*w & 0xffff0000) | (0x100 << n);
+ }
#endif /* CONFIG_MIPS_MT_SMTC */
w = (u32 *)(b + lui_offset);
*w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
@@ -1383,6 +1385,13 @@ void __init per_cpu_trap_init(void)
cpu_cache_init();
tlb_init();
#ifdef CONFIG_MIPS_MT_SMTC
+ } else if(!secondaryTC) {
+ /*
+ * First TC in non-boot VPE must do subset of tlb_init()
+ * for MMU countrol registers.
+ */
+ write_c0_pagemask(PM_DEFAULT_MASK);
+ write_c0_wired(0);
}
#endif /* CONFIG_MIPS_MT_SMTC */
}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index f0366af..2f73c34 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -51,6 +51,8 @@
#include <asm/mips-boards/seadint.h>
#endif
+#define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
+
unsigned long cpu_khz;
static int mips_cpu_timer_irq;
