On Donnerstag, 8. Februar 2007, Thomas Gleixner wrote:
> > +/* command and control functions */
> > +static void excite_nand_control(struct mtd_info *mtd, int cmd,
> > + unsigned int ctrl)
> > +{
> > + io_reg_t regs =
> > + container_of(mtd, struct excite_nand_drvdata, board_mtd)->regs;
> > + static void __iomem *tgt = NULL;
> > +
> > + switch (ctrl) {
> > + case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
> > + tgt = regs + EXCITE_NANDFLASH_CMD_BYTE;
> > + break;
> > + case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
> > + tgt = regs + EXCITE_NANDFLASH_ADDR_BYTE;
> > + break;
> > + case NAND_CTRL_CHANGE | NAND_NCE:
> > + tgt = regs + EXCITE_NANDFLASH_DATA_BYTE;
> > + break;
> > + }
>
> Err, did this ever work ? I doubt it. From nand_base.c:
>
> chip->cmd_ctrl(mtd, page_addr, ctrl);
> ctrl &= ~NAND_CTRL_CHANGE;
> chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
>
> So I expect an OOPS happens on a regular base.
>
I guess it is the 'static void __iomem *tgt = NULL' part that worries
you? Think about it, that value is never used.
However, I admit it is somewhat unclean, and therefore I am changing
it. Updated patch follows.
tk
