Hello.
Vitaly Wool wrote:
the patch inlined below restores proper time accounting for PNX8550-based boards. It also gets rid of #ifdef in the generic code which becomes unnecessary then.
Signed-off-by: Vitaly Wool <vwool@xxxxxxxxxxxxx>
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 11aab6d..5fe3eb8 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -94,10 +94,8 @@ static void c0_timer_ack(void)
{
unsigned int count;
-#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */
/* Ack this timer interrupt and set the next one. */
expirelo += cycles_per_jiffy;
-#endif
write_c0_compare(expirelo);
/* Check to see if we have missed any timer interrupts. */
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 65c440e..25a8df7 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -29,12 +29,27 @@
#include <asm/hardirq.h>
#include <asm/div64.h>
#include <asm/debug.h>
+#include <asm/time.h>
#include <int.h>
#include <cm.h>
extern unsigned int mips_hpt_frequency;
This is already declared in <asm/time.h>...
+static unsigned long cpj;
+
+static cycle_t hpt_read(void)
+{
+ return read_c0_count2();
+}
+
+static void timer_ack(void)
+{
+ write_c0_compare(cpj);
+}
+
+extern struct clocksource clocksource_mips;
And this too...
@@ -68,22 +83,41 @@ void pnx8550_time_init(void)
* HZ timer interrupts per second.
*/
mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
+ cpj = (mips_hpt_frequency + HZ / 2) / HZ;
+ timer_ack();
Probably makes sense to clear Count2 as well...
void __init plat_timer_setup(struct irqaction *irq)
{
int configPR;
setup_irq(PNX8550_INT_TIMER1, irq);
+ setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
/* Start timer1 */
configPR = read_c0_config7();
configPR &= ~0x00000008;
write_c0_config7(configPR);
- /* Timer 2 stop */
+ /* Timer 2 start */
configPR = read_c0_config7();
- configPR |= 0x00000010;
+ configPR &= ~0x00000010;
write_c0_config7(configPR);
I'd have coalesced that into one RMW but well...
write_c0_count2(0);
WBR, Sergei
