On Tue, 12 Dec 2006 17:18:10 +0000, Thiemo Seufer <ths@xxxxxxxxxxxx> wrote: > > +#define odd t5 > > +#define errptr t6 > > Does this work for 64 bit? t5/t6/t7 look weird for that. Yes. I tested on 32/64 bit, little/big endian. Excerpt from head of csum_partial.S (or memcpy.S): #ifdef CONFIG_64BIT /* * As we are sharing code base with the mips32 tree (which use the o32 ABI * register definitions). We need to redefine the register definitions from * the n64 ABI register naming to the o32 ABI register naming. */ #undef t0 #undef t1 #undef t2 #undef t3 #define t0 $8 #define t1 $9 #define t2 $10 #define t3 $11 #define t4 $12 #define t5 $13 #define t6 $14 #define t7 $15 --- Atsushi Nemoto
