Hi,
I am new to MIPS and uclinux port.I am getting familiarised with 2.6.18
linux code.
I see the following code in asm/mips/kernel/genex.S &
asm/mips/kernel/traps.c
++++++++++++ Genex.S +++++++++++++
NESTED(except_vec3_generic, 0, sp)
.set push
.set noat
#if R5432_CP0_INTERRUPT_WAR
mfc0 k0, CP0_INDEX
#endif
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
#ifdef CONFIG_64BIT
dsll k1, k1, 1
#endif
PTR_L k0, exception_handlers(k1)
jr k0
.set pop
END(except_vec3_generic)
+++++++++++++ traps.c +++++++++++++++
set_except_vector(0, handle_int);
set_except_vector(1, handle_tlbm);
set_except_vector(2, handle_tlbl);
set_except_vector(3, handle_tlbs);
set_except_vector(4, handle_adel);
set_except_vector(5, handle_ades);
set_except_vector(6, handle_ibe);
set_except_vector(7, handle_dbe);
set_except_vector(8, handle_sys);
set_except_vector(9, handle_bp);
set_except_vector(10, handle_ri);
set_except_vector(11, handle_cpu);
set_except_vector(12, handle_ov);
set_except_vector(13, handle_tr);
In R3000 manual , bits 2-6 indicate exception code value. In genex.S ,
the cause register is anded with 0x7c to extract 2-6 bits.
I am not able to understand why it is not shifted the last 2 bits.
Please try to educate me why this is not done.
Ramgopal Kota
