This patch shows you more details about the cache using /proc/cpuinfo.
It also shows the TLB page size.
For example:
system type : MIPS Malta
processor : 0
cpu model : MIPS 20Kc V2.0 FPU V2.0
BogoMIPS : 478.20
wait instruction : no
microsecond timers : yes
tlb_entries : 48 64K pages
icache size : 32K sets 256 ways 4 linesize 32
dcache size : 32K sets 256 ways 4 linesize 32
default cache policy : cached write-back
extra interrupt vector : yes
hardware watchpoint : yes
ASEs implemented : mips3d
VCED exceptions : not available
VCEI exceptions : not available
Date: Thu, 14 Sep 2006 11:24:51 -0400
Subject: [PATCH] Add cache info to cpuinfo display.
---
arch/mips/kernel/proc.c | 34 +++++++++++++++++++++++++++++++++-
1 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index d8beef1..54f4da3 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -92,6 +92,7 @@ static int show_cpuinfo(struct seq_file
unsigned int version = current_cpu_data.processor_id;
unsigned int fp_vers = current_cpu_data.fpu_id;
unsigned long n = (unsigned long) v - 1;
+ unsigned long cache_size;
char fmt [64];
#ifdef CONFIG_SMP
@@ -118,7 +119,38 @@ #endif
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no");
- seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize);
+ seq_printf(m, "tlb_entries\t\t: %d %luK pages\n", current_cpu_data.tlbsize,
+ PAGE_SIZE/1024);
+ cache_size = current_cpu_data.icache.sets *
+ current_cpu_data.icache.ways *
+ current_cpu_data.icache.linesz;
+ if (cache_size) {
+ seq_printf(m, "icache size\t\t: %luK sets %d ways %d linesize %d\n",
+ cache_size/1024, current_cpu_data.icache.sets,
+ current_cpu_data.icache.ways, current_cpu_data.icache.linesz);
+ }
+ cache_size = current_cpu_data.dcache.sets *
+ current_cpu_data.dcache.ways *
+ current_cpu_data.dcache.linesz;
+ if (cache_size) {
+ seq_printf(m, "dcache size\t\t: %luK sets %d ways %d linesize %d\n",
+ cache_size/1024, current_cpu_data.dcache.sets,
+ current_cpu_data.dcache.ways, current_cpu_data.dcache.linesz);
+ }
+ cache_size = current_cpu_data.scache.sets *
+ current_cpu_data.scache.ways *
+ current_cpu_data.scache.linesz;
+ if (cache_size) {
+ seq_printf(m, "scache size\t\t: %luK sets %d ways %d linesize %d\n",
+ cache_size/1024, current_cpu_data.scache.sets,
+ current_cpu_data.scache.ways, current_cpu_data.scache.linesz);
+ }
+ /* In pgtable-bits.h we never use a write-through policy */
+#ifdef CONFIG_MIPS_UNCACHED
+ seq_printf(m, "default cache policy\t: uncached\n");
+#else
+ seq_printf(m, "default cache policy\t: cached write-back\n");
+#endif
seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s\n",
--
1.4.1
