Atsushi Nemoto wrote:
[snip]
> @@ -375,6 +376,72 @@ #endif
> BUILD_HANDLER dsp dsp sti silent /* #26 */
> BUILD_HANDLER reserved reserved sti verbose /* others */
>
> + .align 5
> + LEAF(handle_ri_rdhwr_vivt)
> +#ifdef CONFIG_MIPS_MT_SMTC
> + PANIC_PIC("handle_ri_rdhwr_vivt called")
> +#else
> + .set push
> + .set noat
> + .set noreorder
> + /* check if TLB contains a entry for EPC */
> + MFC0 k1, CP0_ENTRYHI
> + andi k1, 0xff /* ASID_MASK */
> + MFC0 k0, CP0_EPC
> + PTR_SRL k0, PAGE_SHIFT + 1
> + PTR_SLL k0, PAGE_SHIFT + 1
> + or k1, k0
> + MTC0 k1, CP0_ENTRYHI
> + mtc0_tlbw_hazard
> + tlbp
This needs a .set mips3/.set mips0 pair.
> +#ifdef CONFIG_CPU_MIPSR2
> + _ehb /* tlb_probe_hazard */
> +#else
> + nop; nop; nop; nop; nop; nop /* tlb_probe_hazard */
> +#endif
What about a mtc0_tlbp_hazard macro here?
Thiemo
