On Mon, Aug 21, 2006 at 04:51:40PM +0200, Geert Uytterhoeven wrote: > Or become fully configurable, to make it match every single MIPS core ever > build? I imagine a special debug CPU type that throws exception when particular problems such as cache aliases, stale I-cache lines, back-to-back cp0 operations and other dangerous or suspisious instructions are detected or more complex and detailed profiling that a processor can offer. Ralf
