On Sat, Jul 08, 2006 at 01:43:39AM +0900, Atsushi Nemoto wrote: > > > For a VIVT I-cache this can result in a TLB exception. TLB handlers are > > > not currently prepared for being called at the exception level. > > > > Thanks, now I understand the problem. Are there any good solutions? > > Only I can think now is using handle_ri_slow for such CPUs. > > Can we use Index_Load_Data_I to load the instruction code from icache? > Just an idea... In addition to what Maciej said - the format of instructions in the I-cache is not necessarily the same as in memory. Many processor store pre-decoded instructions in the I-cache. Ralf
