Hello. Rodolfo Giometti wrote:
AND make sure every buffer/TD/ED is written back / invalidated from cache before the OHCI accesses them since the cache coherency on Au1xx0 is b0rken!
Or, better yet, access TD/ED (and, if possible, the buffers) via uncached KSEG1 only.
Mmm... good suggestion! :) How can I invalidated the cache? Can you please show me some example code?
Dig in arch/mips/mm/c-r4k.c...
Thanks _a lot_! Rodolfo
WBR, Sergei
