Hi Rodolfo, On Thu, Apr 27, 2006 at 05:49:48PM +0200, Rodolfo Giometti wrote: > I noticed that the serial lines management code is changed from > linux-2.6.12 and I'd like to know if someone is running the serial > console on ttyS0 on au1100... Can it be that you face the same problem I was facing not so long ago? After I applied the patch in the email I attach to this one all my serial troubles on the au1100 disappeared. At the moment I'm running kernel 2.6.16 and am using a serial console and several other serial applications without any problem. So, please find attached two emails. One is the answer I received on sort of like the same question like you pose right now and the other is the improved patch by Jon that fixed the problem for me. -- $ cat ~/.signature Freddy Spierenburg <freddy@xxxxxxxxxxxxxxx> http://freddy.snarl.nl/ GnuPG: 0x7941D1E1=C948 5851 26D2 FA5C 39F1 E588 6F17 FD5D 7941 D1E1 $ # Please read http://www.ietf.org/rfc/rfc2015.txt before complain!
--- Begin Message ---
- To: Freddy Spierenburg <freddy@xxxxxxxxxxxxxxx>
- Subject: Re: UART trouble on the DBAu1100
- From: Domen Puncer <domen.puncer@xxxxxxxx>
- Date: Fri, 14 Apr 2006 08:06:41 +0200
- Cc: linux-mips@xxxxxxxxxxxxxx
- Delivered-to: freddy@xxxxxxxx
- In-reply-to: <20060413131117.GP11097@xxxxxxxxxxxxxxx>
- References: <20060413131117.GP11097@xxxxxxxxxxxxxxx>
- User-agent: Mutt/1.5.11
On 13/04/06 15:11 +0200, Freddy Spierenburg wrote: > Hi, > > I have a problem and yet am not sure where to look. It's a > problem in the serial driver for the internal UART's of the > AU1100. It appeared ever since 2.6.15. 2.6.14 is working like a > charm, but 2.6.15 gives me the trouble. > > When I open a tty with the open(2) system call (see attached open.c) > I see that the UART sends a 0x36 byte on the line. We had the same problem on Au1200, applying http://www.linux-mips.org/archives/linux-mips/2006-03/msg00259.html (or maybe a different version of this patch) fixed it. > > But that's not the only trouble. I also do not receive any > bytes received by the UART. All the received bytes stay > in the input buffer of the UART only to be send up to userland > as soon as the UART is asked to send a byte on the line itself. > Then in one take all the bytes are received by the application > listening. I may be way off, but maybe it's just flow control that needs to be turned off. Domen
--- End Message ---
--- Begin Message ---
- To: rmk+serial@xxxxxxxxxxxxxxxx
- Subject: [PATCH] serial8250: set divisor register correctly for AMD Alchemy SoC uart. 3rd edition.
- From: Jon Anders Haugum <jonah@xxxxxxxxxxxxxx>
- Date: Thu, 20 Apr 2006 14:55:59 +0200 (CEST)
- Cc: linux-serial@xxxxxxxxxxxxxxx, linux-mips@xxxxxxxxxxxxxx
- Delivered-to: freddy@xxxxxxxx
Alchemy SoC uart have got a non-standard divisor register that needs some special handling. This patch adds divisor read/write functions with test and special handling for Alchemy internal uart. Signed-off-by: Jon Anders Haugum <jonah@xxxxxxxxxxxxxx> --- 3rd edition: - Removed section covering 16C850 autoconfig. --- linux-2.6.16-rc5/drivers/serial/8250.c.orig 2006-03-03 02:12:10.000000000 +0100 +++ linux-2.6.16-rc5/drivers/serial/8250.c 2006-03-03 02:16:19.000000000 +0100 @@ -362,6 +362,40 @@ serial_out(struct uart_8250_port *up, in #define serial_inp(up, offset) serial_in(up, offset) #define serial_outp(up, offset, value) serial_out(up, offset, value) +/* Uart divisor latch read */ +static inline int _serial_dl_read(struct uart_8250_port *up) +{ + return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; +} + +/* Uart divisor latch write */ +static inline void _serial_dl_write(struct uart_8250_port *up, int value) +{ + serial_outp(up, UART_DLL, value & 0xff); + serial_outp(up, UART_DLM, value >> 8 & 0xff); +} + +#ifdef CONFIG_SERIAL_8250_AU1X00 +/* Au1x00 haven't got a standard divisor latch */ +static int serial_dl_read(struct uart_8250_port *up) +{ + if (up->port.iotype == UPIO_AU) + return __raw_readl(up->port.membase + 0x28); + else + return _serial_dl_read(up); +} + +static void serial_dl_write(struct uart_8250_port *up, int value) +{ + if (up->port.iotype == UPIO_AU) + __raw_writel(value, up->port.membase + 0x28); + else + _serial_dl_write(up, value); +} +#else +#define serial_dl_read(up) _serial_dl_read(up) +#define serial_dl_write(up, value) _serial_dl_write(up, value) +#endif /* * For the 16C950 @@ -494,7 +528,8 @@ static void disable_rsa(struct uart_8250 */ static int size_fifo(struct uart_8250_port *up) { - unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr; + unsigned char old_fcr, old_mcr, old_lcr; + unsigned short old_dl; int count; old_lcr = serial_inp(up, UART_LCR); @@ -505,10 +540,8 @@ static int size_fifo(struct uart_8250_po UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_outp(up, UART_MCR, UART_MCR_LOOP); serial_outp(up, UART_LCR, UART_LCR_DLAB); - old_dll = serial_inp(up, UART_DLL); - old_dlm = serial_inp(up, UART_DLM); - serial_outp(up, UART_DLL, 0x01); - serial_outp(up, UART_DLM, 0x00); + old_dl = serial_dl_read(up); + serial_dl_write(up, 0x0001); serial_outp(up, UART_LCR, 0x03); for (count = 0; count < 256; count++) serial_outp(up, UART_TX, count); @@ -519,8 +552,7 @@ static int size_fifo(struct uart_8250_po serial_outp(up, UART_FCR, old_fcr); serial_outp(up, UART_MCR, old_mcr); serial_outp(up, UART_LCR, UART_LCR_DLAB); - serial_outp(up, UART_DLL, old_dll); - serial_outp(up, UART_DLM, old_dlm); + serial_dl_write(up, old_dl); serial_outp(up, UART_LCR, old_lcr); return count; @@ -750,8 +780,7 @@ static void autoconfig_16550a(struct uar serial_outp(up, UART_LCR, 0xE0); - quot = serial_inp(up, UART_DLM) << 8; - quot += serial_inp(up, UART_DLL); + quot = serial_dl_read(up); quot <<= 3; status1 = serial_in(up, 0x04); /* EXCR1 */ @@ -759,8 +788,7 @@ static void autoconfig_16550a(struct uar status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ serial_outp(up, 0x04, status1); - serial_outp(up, UART_DLL, quot & 0xff); - serial_outp(up, UART_DLM, quot >> 8); + serial_dl_write(up, quot); serial_outp(up, UART_LCR, 0); @@ -1862,8 +1890,7 @@ serial8250_set_termios(struct uart_port serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ } - serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ - serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ + serial_dl_write(up, quot); /* * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
--- End Message ---
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