Dear Mr. Seufer, Thank you for your advice about directives. That's exactly what I meant. I have confused them with push/pop style operations. Thanks. Regards, JS. -----Original Message----- From: Thiemo Seufer [mailto:ths@xxxxxxxxxxxx] Sent: Wednesday, April 26, 2006 7:16 PM To: Kim, Jong-Sung Cc: linux-mips@xxxxxxxxxxxxxx Subject: Re: Reading an entire cacheline Kim, Jong-Sung wrote: > Hi all, > > Please look at following codes: > > save_flags(flags); > cli(); > __asm__ __volatile__( > " .set noreorder\n" > " .set mips32\n" > "2: .set mips3\n" > " cache 5, 0x00(%12)\n" > " .set mips0\n" Irrelevant sidemark: .set mips0 resets to the original value, not to mips32. You probably want .set push .set noreorder .set mips32 ... <the whole code sequence> .set pop [snip] > //" bne %0, %9, 2b\n" > " .set mips0\n" > " .set reorder" > : "=r" (tag[1][way][0]), "=r" (datalo[1][way][0]), > "=r" (datahi[1][way][0]), > "=r" (tag[1][way][1]), "=r" (datalo[1][way][1]), > "=r" (datahi[1][way][1]), > "=r" (tag[1][way][2]), "=r" (datalo[1][way][2]), > "=r" (datahi[1][way][2]), > "=r" (tag[1][way][3]), "=r" (datalo[1][way][3]), > "=r" (datahi[1][way][3]) > : "r" (0x80000000 | (way << 14) | (line << 5)) > ); And this part may cause the problem you are seeing, I presume datalo/datahi live in memory, and accesses of it change the dcache. As Kevin mentioned, disassembling the binary might be helpful. Thiemo
