Hi all, Was my question too brief? I'm using MIPS5Kf core included in a Broadcom implemented processor and it has a 32kB d-cache and a same sized i-cache. Cache configuration is 2-way, 32-byte cacheline for both d- and i-cache without L2 cache. Of course, MIPS-port Linux as the kernel for it. And, a onboard block device has problem in its operation. I don't think it's a kernel problem. So I wanna inspect the contents of cache RAMs at the device driver's context. I've added some lines of codes look like follow: __asm__ __volatile__( ".set noreorder\n\t" ".set mips3\n\t" "cache 5, 0x00(%3)\n\t" // load d-cache tag ".set mips0\n\t" // by index ".set mips32\n\t" "mfc0 %0, $28, 0\n\t" "mfc0 %1, $28, 1\n\t" "mfc0 %2, $29, 1\n\t" .set mips0\n\t" .set reorder" : "=r" (tag), "=r" (data_lo), "=r" (data_hi) : "r" (0x80000000 | (way << 14) | (index << 5) | (word << 3)) ); This is executed for every index, every way, and every word. The thing aches my head is the tags from a single cacheline differs. (very often for d-cache) So I modified the code to reread the cacheline from the first word when the tag was modified before reading all four words. Then the code never return. I couldn't find any related information from manual. Please give me a hint for reading whole cacheline safely. -----Original Message----- From: linux-mips-bounce@xxxxxxxxxxxxxx [mailto:linux-mips-bounce@xxxxxxxxxxxxxx] On Behalf Of Kim, Jong-Sung Sent: Tuesday, April 18, 2006 9:37 AM To: linux-mips@xxxxxxxxxxxxxx Subject: Reading an entire cacheline Hi, Is there any way to read an entire cacheline from the MIPS5Kf? Four sequential cache instructions do similarly, but sometimes the tags from a same cacheline differ. How can I read a consistent cacheline safely? Thanks.
