I'm running into a random problem with a mips64 kernel (2.6.14 based). I
see the problem on the MIPS Malta 5kf board but it seems like a generic
bug to me. What happens is that CP0 FR bit is zero and an add register
is accessed by an instruction whose datatype is 64 bits. That results in
a reserved instruction kernel fault. I see this bug in gdb-low.S - the
code checks to see if CU1 is enabled but then it seems to assume that FR
is always 1 when running a 64bit kernel. However, I also randomly see
the bug without kgdb being enabled when we hit _save_fp and this macro:
.macro fpu_save_double thread status tmp1 tmp2
sll \tmp2, \tmp1, 5
bgez \tmp2, 2f
fpu_save_16odd \thread
2:
fpu_save_16even \thread \tmp1 # clobbers t1
.endm
tmp1 is "t0" and it's not clear to me why we're checking t0 instead of
status in order to decide whether to save the odd registers or not. I
must be missing something because others would have hit this bug by now.
Any clues would be appreciated.
Thanks,
Pete
