Hi Ralf, Thanks for the reply. >Correct. So if at all you would have to rip oprofile from the >2.6 kernel and bolt that code back into the old kernel which >would seem doable. The MIPS bits certainly don't rely on much >2.6 infrastructure. #1: I looked at oprofile-0.9.1 and it lists this event for SB1 in the events/mips/sb1 directory ------------------------------------------------------------------------ --- event:10 counters:1,2,3 um:zero minimum:500 name:DCACHE_FILLED_SHD_NONC_EXC :Dcache is filled (shared, nonc, exclusive) ---------------------------------------------------------------- However this doesn't have an equivalent performance source Listed in the sibyte manual (table 33 system performance counter sources). #2: how does the mapping from event numbers to performance sources work for sibyte ? I looked at the op_model_mipsxx.c file in the 2.6 CVS tree and the macro it uses doesn't seem to match the format specified for perf_cnt_cfg register in sibyte. What am I missing ? Thx Kiran
