On Wed, Feb 22, 2006 at 09:25:39PM +0100, Thomas Koeller wrote: > The ll/sc versions of atomic_sub_if_positive(), and the corresponding 64-bit functions, > are broken. The value returned by those functions is always one, no matter what. Good catch - and I wonder how you found this bug since it didn't seem to cause any obvious damage. I just went for a different fix though - I was able to get away without an extra register and squeeze the needed extra instruction into a delay slot, so no code size penalty either. Ralf Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -250,7 +250,10 @@ static __inline__ int atomic_sub_if_posi " subu %0, %1, %3 \n" " bltz %0, 1f \n" " sc %0, %2 \n" + " .set noreorder \n" " beqzl %0, 1b \n" + " subu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -266,7 +269,10 @@ static __inline__ int atomic_sub_if_posi " subu %0, %1, %3 \n" " bltz %0, 1f \n" " sc %0, %2 \n" + " .set noreorder \n" " beqz %0, 1b \n" + " subu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -598,7 +604,10 @@ static __inline__ long atomic64_sub_if_p " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" " scd %0, %2 \n" + " .set noreorder \n" " beqzl %0, 1b \n" + " dsubu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n" @@ -614,7 +623,10 @@ static __inline__ long atomic64_sub_if_p " dsubu %0, %1, %3 \n" " bltz %0, 1f \n" " scd %0, %2 \n" + " .set noreorder \n" " beqz %0, 1b \n" + " dsubu %0, %1, %3 \n" + " .set reorder \n" " sync \n" "1: \n" " .set mips0 \n"
