On Thu, Feb 02, 2006 at 09:46:25PM +0300, Sergei Shtylylov wrote: > Atsushi Nemoto wrote: > >If mfc0 $12 follows store and the mfc0 is last instruction of a > >page and fetching the next instruction causes TLB miss, the result > >of the mfc0 might wrongly contain EXL bit. > > Hmm, a TLB miss in fetching from KSEG0?! It'll hit loadable modules which run in the mapped KSEG2/3 spaces. Ralf
