[PATCH] local_r4k_flush_cache_page fix

[Atsushi Nemoto <anemo@xxxxxxxxxxxxx>]

If dcache_size != icache_size or dcache_size != scache_size,
icache/scache does not flushed properly.  Use correct cache size to
calculate index value for scache/icache.

Signed-off-by: Atsushi Nemoto <anemo@xxxxxxxxxxxxx>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index e51c38c..d70d700 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -376,6 +376,7 @@ static inline void local_r4k_flush_cache
 	struct flush_cache_page_args *fcp_args = args;
 	struct vm_area_struct *vma = fcp_args->vma;
 	unsigned long addr = fcp_args->addr;
+	unsigned long index;
 	int exec = vma->vm_flags & VM_EXEC;
 	struct mm_struct *mm = vma->vm_mm;
 	pgd_t *pgdp;
@@ -425,11 +426,13 @@ static inline void local_r4k_flush_cache
 	 * Do indexed flush, too much work to get the (possible) TLB refills
 	 * to work correctly.
 	 */
-	addr = INDEX_BASE + (addr & (dcache_size - 1));
 	if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-		r4k_blast_dcache_page_indexed(addr);
-		if (exec && !cpu_icache_snoops_remote_store)
-			r4k_blast_scache_page_indexed(addr);
+		index = INDEX_BASE + (addr & (dcache_size - 1));
+		r4k_blast_dcache_page_indexed(index);
+		if (exec && !cpu_icache_snoops_remote_store) {
+			index = INDEX_BASE + (addr & (scache_size - 1));
+			r4k_blast_scache_page_indexed(index);
+		}
 	}
 	if (exec) {
 		if (cpu_has_vtag_icache) {
@@ -437,8 +440,10 @@ static inline void local_r4k_flush_cache
 
 			if (cpu_context(cpu, mm) != 0)
 				drop_mmu_context(mm, cpu);
-		} else
-			r4k_blast_icache_page_indexed(addr);
+		} else {
+			index = INDEX_BASE + (addr & (icache_size - 1));
+			r4k_blast_icache_page_indexed(index);
+		}
 	}
 }