This patch uses 'wsbh' instruction to optimize swab operations. This
instruction is part of the MIPS Release 2 instructions set.
Signed-off-by: Franck BUI-HUU <vagabon.xyz@xxxxxxxxx>
---
include/asm-mips/byteorder.h | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+), 0 deletions(-)
4dc5b8c501404d1d133e45ea99f1cd54bbb8e37f
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index d1fe9e5..f9f5059 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -8,10 +8,37 @@
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
+#include <linux/compiler.h>
#include <asm/types.h>
#ifdef __GNUC__
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__(
+ "wsbh %0, %1\n"
+ : "=r" (x)
+ : "r" (x));
+ return x;
+}
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__(
+ "wsbh %0, %1\n\t"
+ "rotr %0, %0, 16\n"
+ : "=r" (x)
+ : "r" (x));
+ return x;
+}
+
+#define __arch__swab16(x) ___arch__swab16(x)
+#define __arch__swab32(x) ___arch__swab32(x)
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
