> On Tue, 17 Jan 2006, Bharathi Subramanian wrote:
>
> > On Mon, 16 Jan 2006, Bharathi Subramanian wrote:
> >
> > > We are trying to implement the CPU Clock down feature for saving the
> > > power. In this process, Whenever the CPU is put in 1/2 Clock then the
> > > Timer interrupt is also getting delayed.
> > >
> > > Later I found that CPU Counter is used to generate the timer intr. How
> > > to make the Timer interrupt to happen at every 10ms, even if the CPU
> > > is in 1/2, 1/4 or 1/8 of the original clock??
> > >
> > > Processor: MIPS 4Kc 32B
> > Kernel : 2.4.20 with RTLinux Patch
> >
> > In mips_timer_ack() function, the new Compare reg value loaded. Here I
> > tried to put new counter value based on the present cpu clock divder
> > setting. But board is getting rebooted.
> >
> > Is it the right way to handle this issue?? Anybody faced same
> > condition, kindly share your exprience with me.
>
> I read the Linux Porting guide by Junsun. In that,(s)he mention, "Some
> CPUs may have a variable CPU frequency which makes CPU counter not
> usable as a timer source". Does it mean that, we can't do the CPU
> Clock down in MIPS Processor??
Some systems have variable CPU frequencies that are invisible to software,
in which case a CPU counter would not be very usefule as a timer source.
If your CPU clock mode is programmable, as it is on most MIPS systems
of which I'm aware, it just means that you have to keep your Count register
programming synchronized with the clock mode.
You were on the right track when you tried hacking mips_timer_ack(),
but note that both cycles_per_jiffy and mips_hpt_frequency end up being
used in Count-based time calculations. If the board is rebooting when you
tested your mod, it's probably because there's an error or a typo in your code.
Note that just changing the Count register increment will result in some
small error each time the clock mode changes, because the new increment
won't take effect until the next interrupt goes off. which will be some random
interval after the CPU clock divisor has changed. If that's a real issue,
you can reduce the error to a few cycles if you really want to go to the
trouble of sampling the Count register and re-computing the Compare value
when you change the CPU clock mode.
Regards,
Kevin K.
